An Empirical and Analytical Comparison of Delay Elements and a New Delay Element Design
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
An analysis of the robustness of CMOS delay elements
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
EURASIP Journal on Applied Signal Processing
Interconnect customization for a hardware fabric
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a low-power CMOS thyristor based delay element for inclusion in standard cell ASIC libraries, and a reconfigurable delay element designed for reconfigurable devices. Our design is based on a basic delay element, which serves as a buffer which has been specially designed to have a fixed propagation delay. We present leakage power optimizations, which when applied to the circuit reduces the on-state leakage power consumption by more than 99%, while reducing the off-state leakage power by roughly 96%. We have created delay elements with delay lengths of 4, 5, 7, 9, 11, and 17 ns for inclusion in a standard cell library targeting the IBM 0.13 μm technology. The delay element is then further extended to introduce a programmability feature which allows the delay to be varied. Two reconfigurable delay elements are then added to the delay element standard cell library. The first can be configured for delays of 4, 5, or 7 ns, while the second can be programmed for delays of 9, 11, or 17 ns. Finally, potential uses of the circuits in application specific, as well as reconfigurable systems are explored.