Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A low-power CMOS thyristor based delay element with programmability extensions
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we review three different families of delay elements used in CMOS VLSI design: (1) transmission gate based, (2) cascaded inverter based, and (3) voltage-controlled ones. We compare their effectiveness in terms of yield, which is defined as the number of delay elements that have delays within a specified delay range. The delay variations are obtained through HSpice Monte Carlo simulations and are analyzed using analytical delay expressions. The sensitivity of the delay elements to different process and environmental variations can be studied using the simulation results. This will enable designers to select the best delay element for their design and also do a robust design by taking into account the sensitivities of delay elements to different parameters.