DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Proceedings of the 1995 international symposium on Low power design
Low Power Design Symposium
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
Low Power Digital CMOS Design
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Low-Power Design by Hazard Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Input-specific dynamic power optimization for VLSI circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In the previous work, the problem of finding gatedelays to eliminate glitches has been solved by linearprograms (LP) requiring an exponentially largenumber of constraints. By introducing two additionalvariables per gate, namely, the fastest and the slowestarrival times, besides the gate delay, we reduce thenumber of the LP constraints to be linear in circuitsize. For example, the 469-gate c880 circuit requires3,611 constraints as compared to the 6.95 million constraintsneeded with the previous method. The reducedconstraints provably produce the same exactLP solution as obtained by the exponential set of constraints.For the first time, we are able to optimize allISCAS'85 benchmarks. For the c7552 circuit, whenthe input to output delay is constrained not to increase,a design with 366 delay buffers consumes only34% peak and 38% average po er as compared toan unoptimized design. As shown in previous work,the use of delay buffers is essential in this case. Thepracticality of the design is demonstrated by implementingan optimized 4-bit ALU circuit for which thepower consumption as obtained by a circuit-levelsimulator.