Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
The essence of logic circuits
Low Power Digital CMOS Design
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A graph approach to DFT hardware placement for robust delay fault BIST
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Input-specific dynamic power optimization for VLSI circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Before signals of a digital circuit reach steady state, gates can have multiple transitions. Since the power is dissipated in a CMOS circuit mainly due to transitions, the extra transitions increase power consumption. These transitions are the hazard pulses generated by a logic gate when signals arrive by paths of varying delays. The maximum width of a hazard pulse produced by a gate is the maximum difference between the delays of incident paths, which is generally much smaller than the clock period. We propose suppression of hazard pulses by increasing the delays of gates where hazards could have been generated. Thus, a hazard filtering gate has a delay which is at least as much as the differential delay of its input paths. We give examples to illustrate the novel technique and also indicate that the overall reduction in the circuit speed may not be too much with proper sizing of transistors, while there can be a significant reduction in power consumption.