Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Practical low power digital VLSI design
Practical low power digital VLSI design
Glitch power minimization by gate freezing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low Power Design in Deep Submicron Electronics
Low Power Design in Deep Submicron Electronics
Low-Power CMOS Design
Low Power Digital CMOS Design
Power Aware Design Methodologies
Power Aware Design Methodologies
Optimizing CMOS Circuits for Low Power Using Transistor Reordering
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Low-Power Design by Hazard Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Minimum dynamic power cmos design with variable input delay logic
Minimum dynamic power cmos design with variable input delay logic
Variable Input Delay CMOS Logic for Low Power Design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called variable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.