Proceedings of the 2006 international symposium on Low power electronics and design
Input-specific dynamic power optimization for VLSI circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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A new low-power design method producesCMOS circuits that consume the least dynamic powerat the highest speed permitted under the technologyconstraint.A gate is characterized by an inertial delayand separate delays between its inputs and output.The technology constraint, related to feasible rangesof lengths and widths of transistors, is specified by aparameter ub.It is the upper bound on the differencebetween the inputs of a gate.We formulate a linearprogram (LP) whose size is proportional to the circuitsize.This LP determines the inertial delay as well asinput to output delays for each gate of the circuit withthe given ub, such that all glitches are eliminated andthe overall delay of the circuit is minimized.Becauseof the additional flexibility in specifying gate delays,the glitch suppression is guaranteed without any delaybuffers.Hence this design consumes less powerthan those designed by other methods.We designedthe circuit c1355 with 46% of the original power dissipationcompared to a reference design.A previouslypublished method, that characterizes each gate with asingle delay, produced a c1355 circuit consuming 58%of the original power.Both low-power circuits had the same overall delay.The previous design required 224delay buffers, whereas the new design needed none.