Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
LP based cell selection with constraints of timing, area, and power consumption
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Extreme delay sensitivity and the worst-case switching activity in VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A power optimization method considering glitch reduction by gate sizing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Practical methodology of post-layout gate sizing for 15% more power saving
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using negative edge triggered ffs to reduce glitching power in FPGA circuits
Proceedings of the 44th annual Design Automation Conference
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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