On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Switching activity analysis and pre-layout activity prediction for FPGAs
Proceedings of the 2003 international workshop on System-level interconnect prediction
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Analysis and reduction of glitches in synchronous networks
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decomposition-based vectorless toggle rate computation for FPGA circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA glitch power analysis and reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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This paper presents an algorithm for reducing dynamic power dissipated by Field-Programmable Gate Array (FPGA) circuits. The algorithm uses a fast probability based model to estimate glitches on wires in a circuit and then inserts negative edge triggered FFs at outputs of Lookup Tables (LUTs) that produce glitches. A negative edge triggered FF maintains the logic value produced by the LUT in the previous cycle for the first half of the clock period, filtering glitches that occur at the output of the LUT. The power dissipation is lowered by reducing the number of transitions that propagate to the general routing network. We applied the algorithm to a set of benchmark circuits implemented on a commercial FPGA, Altera's Stratix II. The results obtained using Quartus II 5.1 CAD tool show a reduction in dynamic power dissipation by 7% on average and up to 25%.