The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A cell-based power estimation in CMOS combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
POSE: power optimization and synthesis environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Technology-dependent transformations for low-power synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
A re-engineering approach to low power FPGA design using SPFD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low power design and its testability
ATS '95 Proceedings of the 4th Asian Test Symposium
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An approach for multilevel logic optimization targeting low power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using negative edge triggered ffs to reduce glitching power in FPGA circuits
Proceedings of the 44th annual Design Automation Conference
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In this article we present a new approach to the problem of local logic transformation for reducing power dissipation in logic circuits. The proposed approach overcomes one of the critical limitations common to the previous approaches of local logic transformations for low power, namely, a sequential greedy transformation that identifies signals with high switching activities and then resynthesizes the signals one by one. Instead, we identify a set of signal lines as a group for logic transformation, and determine an order of transformation of the signals with the maximum reduction of power dissipation in the circuit. As a practically feasible solution to this problem, we develop a power model called a finite state input transition (FIT) model, which allows the efficient measurement of the change of power dissipation of the circuit for every possible sequence of logic transformations among the signal lines. Experimental results show that the proposed approach performs an extensive local logic transformation, reducing power consumption by 33% on average without any increase of circuit delay.