Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A power modeling and characterization method for the CMOS standard cell library
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A power modeling and characterization method for macrocells using structure information
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
IC test using the energy consumption ratio
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Clocking strategies and scannable latches for low power appliacations
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Estimation of Digital Data Paths Using HEAT
IEEE Design & Test
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
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In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. Based on the model, a Cell-Based Power Estimation (CBPE) method is developed to estimate the power dissipation in CMOS combinational circuits. In our technique, we first construct a modified state transition graph called STGPE to model the power consumption behavior of a logic gate. Then, according to the input signal probabilities and transition densities of the logic gate, we perform an efficient method to estimate the expected activity number of each edge in the STGPE. Finally, the energy consumption of a logic gate is calculated by summing the energy consumptions of each edge in STGPE. For a set of benchmark circuits, experimental results show that the power dissipation estimated by CBPE is on average within 10-percent errors as compared to the exact SPICE simulation while the CPU time is more than two order-of-magnitudes faster.