High-speed VLSI arithmetic processor architectures using hybrid number representation
Journal of VLSI Signal Processing Systems - Special issue: 1990 Workshop on VLSI signal processing
A cell-based power estimation in CMOS combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Low-energy CSMT carry generators and binary adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computation error analysis in digital signal processing systems with overscaled supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
The major concerns of VLSI designers in the past were performance, area, reliability and cost. Power was only a secondary issue. In recent years, however, power, area, and speed have become equally important. There are many reasons for this new trend. Primarily, rapid advancement in semiconductor technology over the past decade has enabled designers to integrate many digital CMOS circuits on a single chip. However, the desirability of using these circuits in portable operations has necessitated the development of low-power technology. Portable applications range from desktop computers and audio-video based multimedia products to personal digital assistants and personal communicators. These systems demand both complex functionality and low power, which make their design challenging. The hierarchical energy analysis tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out