High-speed VLSI arithmetic processor architectures using hybrid number representation

HEAT: hierarchical energy analysis tool

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Radix 2 Division with Over-Redundant Quotient Selection

IEEE Transactions on Computers

A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture

Journal of VLSI Signal Processing Systems

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power Estimation of Digital Data Paths Using HEAT

IEEE Design & Test

A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

High-speed arithmetic coder/decoder architectures

ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I