Square-Rooting Algorithms for High-Speed Digital Circuits
IEEE Transactions on Computers
On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Radix-4 Square Rot Without Initial PLA
IEEE Transactions on Computers
IEEE Transactions on Computers
High-speed VLSI arithmetic processor architectures using hybrid number representation
Journal of VLSI Signal Processing Systems - Special issue: 1990 Workshop on VLSI signal processing
High speed computer arithmetic architectures
High speed computer arithmetic architectures
Radix 2 Division with Over-Redundant Quotient Selection
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
A Fast Radix-4 Division Algorithm and its Architecture
IEEE Transactions on Computers
A floating point radix 2 shared division/square root chip
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Fast Division Algorithm for VLSI
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
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This paper presents the VLSI architecture of a shared division/squareroot operator that operates on the mantissas (23-b in length) of singleprecision IEEE 754 1985 std., floating point numbers. The division andsquare root algorithms used in this operator are based on radix 2signed digit representations and operate in a digit-by-digit manner. These two algorithms perform quotient and root digit selection usingtwo most-significant digits of the partial remainder. Previouslyproposed shared division square-root algorithms required more than twomost-significant digits of the partial remainder to be observed duringquotient or root digit selection. Lower the number of digits observed forquotient or root digit selection, faster the operation. Due to this,the algorithms proposed in this scheme are faster than previous schemes. This architecture has been layed out using 1.2 micron 5.0 V CMOS 2 metal process and requires 14.82 mm^2 area. This design requires 15 ns (@ 5.0 V) to generate a digit of the quotient/root. It requires 29 cycles per divide/square root operation from the time the operands are provided at its pin inputs.