Design of a high-speed square root multiply and divide unit
IEEE Transactions on Computers
On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Simple Radix-4 Division with Operands Scaling
IEEE Transactions on Computers
Design of a Radix 4 Division Unit with Simple Selection Table
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
A Fast Division Algorithm for VLSI
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Radix 2 Division with Over-Redundant Quotient Selection
IEEE Transactions on Computers
Division Algorithms and Implementations
IEEE Transactions on Computers
IEEE Transactions on Computers
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture
Journal of VLSI Signal Processing Systems
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling
Journal of VLSI Signal Processing Systems
Proceedings of the 24th ACM International Conference on Supercomputing
Minimizing the complexity of SRT tables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel design of a two operand normalization circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation of variable-precision floating-point arithmetic
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
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In this paper we present a fast radix-4 division algorithm for floating point numbers. This method is based on Svoboda驴s division algorithm and the radix-4 redundant number system. The algorithm involves a simple recurrence with carry-free addition and employs prescaling of the operands. In the proposed divider implementation, each radix-4 digit (belonging to set {驴3, 驴, +3}) of the quotient and partial remainder is encoded using two radix-2 digits (belonging to the set {驴1, 0, +1}) and this leads to hardware simplicity. The quotient digits are determined by observing three most-significant radix-2 digits of the partial remainder and independent of the divisor. The architecture presented for the proposed algorithm is faster than previously proposed radix-4 dividers, which require at least four digits of the partial remainder to be observed to determine quotient digits.