Radix-16 Signed-Digit Division
IEEE Transactions on Computers
Division Algorithms and Implementations
IEEE Transactions on Computers
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Simple Radix-4 Division with Operands Scaling
IEEE Transactions on Computers
Over-Redundant Digit Sets and the Design of Digit-By-Digit Division Units
IEEE Transactions on Computers
A Fast Radix-4 Division Algorithm and its Architecture
IEEE Transactions on Computers
Choices of Operand Truncation in the SRT Division Algorithm
IEEE Transactions on Computers
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
SRT Division Architectures and Implementations
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
IEEE Transactions on Computers
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
Digit Selection for SRT Division and Square Root
IEEE Transactions on Computers
High Speed Redundant Adder and Divider in Output Prediction Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Area-efficient nonrestoring radix-2k division
Digital Signal Processing
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This paper presents an analysis of the complexity of quotient-digit selection tables in SRT division implementations. SRT dividers are widely used in VLSI systems to compute floating-point quotients. These dividers use a fixed number of partial remainder and divisor bits to consult a table to select the next quotient-digit in each iteration. This analysis derives the allowable divisor and partial remainder truncations for radix 2 through radix 32, and it quantifies the relationship between table parameters and the complexity of the tables. Several techniques are presented for further minimizing table complexity. By mapping the tables to a library of standard-cells, delay and area values were measured and are presented for table configurations through radix 32. Several conclusions are drawn based on this data which impacts optimized SRT divider designs.