Division Algorithms and Implementations
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Digital Computer Arithmetic
Minimizing the complexity of SRT tables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an area-efficient twos complement high radix division algorithm and its architecture. The advantage of using high radix division is to generate more quotient bits per iteration while binary division results in one bit per iteration. In the conventional restoring radix-2^k division, the selection of the quotient digit requires the use of all the multiples of the divisor. As a result, the area increases exponentially (area of radix 2^k divider is about 2^k times the area of binary divider) while the speed increases linearly (speed of radix 2^k divider is approximately k times that of binary divider). In this paper, a new algorithm that makes use only of the even multiples of the divisor is proposed. The area is nearly halved since the number of multiples is reduced from 2^k to 2^k^-^1. We use the even multiples rather than the odd ones because the even multiples are easier to generate and some of them are produced by simply shifting the divisor. For example, the even multiples 2D and 4D are generated by shifting D one and two bits to the left, respectively, while the odd multiples 3D and 5D require an addition of D to 2D and D to 4D, respectively.