A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
The Clipper processor: instruction set architecture and implementation
Communications of the ACM
A Systematic Method for Division with High Average Bit Skipping
IEEE Transactions on Computers
Square Rooting Algorithms for Integer and Floating-Point Numbers
IEEE Transactions on Computers
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Decomposition of Complex Multipliers Using Polynomial Encoding
IEEE Transactions on Computers
Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications
IEEE Transactions on Computers
Reconfigurable Buses with Shift Switching: Concepts and Applications
IEEE Transactions on Parallel and Distributed Systems
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mixed-swing quadrail for low power dual-rail domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
The Statistics of Simulating Chaos
Statistics and Computing
MIP-Map Level Selection for Texture Mapping
IEEE Transactions on Visualization and Computer Graphics
Some Results on a SRT Type Division Scheme
IEEE Transactions on Computers
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Light-Weight Framework for Hardware Verification
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Reusable DSP Functions in FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
On-line testing of scalable signal processing architectures using a software test method
ITC '98 Proceedings of the 1998 IEEE International Test Conference
54x54-bit radix-4 multiplier based on modified booth algorithm
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Pipelined area-efficient digit serial divider
Signal Processing
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Area-efficient nonrestoring radix-2k division
Digital Signal Processing
Integration workshop: Expandable arithmetic block macrocell
Integration, the VLSI Journal
Restriction enzyme computation
IWANN'03 Proceedings of the Artificial and natural neural networks 7th international conference on Computational methods in neural modeling - Volume 1
A power-aware variable-precision multiply-accumulate unit
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified booth algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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