A Fast Serial-Parallel Binary Multiplier
IEEE Transactions on Computers
Discrete-time signal processing
Discrete-time signal processing
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Digital Computer Arithmetic
A Single Chip Parallel Multiplier by MOS Technology
IEEE Transactions on Computers
Efficient Wordlength Reduction Techniques for DSP Applications
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Modified booth truncated multipliers
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design of low-error fixed-width modified booth multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhanced-functionality multipliers
Journal of Systems Architecture: the EUROMICRO Journal
Truncated binary multipliers with variable correction and minimum mean square error
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low error and high performance multiplexer-based truncated multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-accuracy fixed-width modified booth multipliers for lossy applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications
Journal of Signal Processing Systems
| Hi-index | 14.98 |
When two numbers are multiplied, a double-wordlength product is produced. In applications where only the single-precision product is required, the double-wordlength result is rounded to single-precision. Hence, in single-precision applications, it is not necessary to compute the least significant part of the product exactly. Instead, it is only necessary to estimate the carries generated in the computation of the least significant part that will ripple into the most significant part of the product. This will produce a single-precision multiplier with significantly reduced circuit complexity. Three novel methods for realizing this class of reduced complexity single-precision multipliers are introduced and their performance analyzed.