Truncated binary multipliers with variable correction and minimum mean square error

Authors:
Nicola Petra;Davide De Caro;Valeria Garofalo;Ettore Napoli;Antonio G. M. Strollo
Affiliations:
Department of Biomedical Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy;Department of Biomedical Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy;Department of Biomedical Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy;Department of Biomedical Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy;Department of Biomedical Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

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Abstract

Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded to reduce complexity, and a suitable compensation function is add:d to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time. A sub optimal compensation function, best suited for hardware implementation, is introduced. Efficient multipliers implementation based on sub-optimal function is discussed. Proposed truncated multipliers are extensively compared with previously proposed circuits. Experimental results, for a 0.18 µm technology, are also presented.