Quadrature direct digital frequency synthesizers using interpolation-based angle rotation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
A direct digital frequency synthesizer based on the quasi- linear interpolation method
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Truncated binary multipliers with variable correction and minimum mean square error
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Direct Digital Synthesizers: Theory, Design and Applications
Direct Digital Synthesizers: Theory, Design and Applications
IEEE Transactions on Computers
A memory-reduced direct digital frequency synthesizer for OFDM receiver systems
IEEE Transactions on Consumer Electronics
A direct digital frequency synthesizer based on two segment fourth-order parabolic approximation
IEEE Transactions on Consumer Electronics
A direct digital frequency synthesizer based on a new form of polynomial approximations
IEEE Transactions on Consumer Electronics
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The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems. The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation. The performance trend provided by the advanced designs that target ASIC technologies is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device. This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR). The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.