Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA
Integration, the VLSI Journal
| Hi-index | 14.98 |
A truncated multiplier is a multiplier with two n bit operands that produces a n bit result. Truncated multipliers discard some of the partial products of a complete multiplier to trade off accuracy with hardware cost. Compared with a conventional multiplier, a truncated multiplier introduces an error on the output whose magnitude depends on the input bits. The maximum value of the error is hardly computable, since it isn't possible to test every possible input and nonexhaustive simulations are very unlikely to provide the actual maximum absolute error value. It is therefore extremely useful to develop methods that provide the maximum error for a truncated multiplier. This paper presents a closed form analytical calculation, for every bit width, of the maximum error for a previously proposed family of truncated multipliers. The considered family of truncated multipliers is particularly important since it is proved to be the design that gives the lowest mean square error for a given number of discarder partial products. With the contribution of this paper, the considered family of truncated multipliers is the only architecture that can be designed, for every bit width, using an analytical approach that allows the a priori knowledge of the maximum error.