On implementing addition in VLSI technology
Journal of Parallel and Distributed Computing
Improved CLA scheme with optimized delay
Journal of VLSI Signal Processing Systems - Special issue: computer arithmetic
Computer Arithmetic
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Design Strategies for Optimal Multiplier Circuits
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Design and Clocking of VLSI Multipliers
Design and Clocking of VLSI Multipliers
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
IEEE Transactions on Computers
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
IEEE Transactions on Computers
Technology Scaling Effects on Multipliers
IEEE Transactions on Computers
Parallel Multiplication Using Fast Sorting Networks
IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
Layout-aware synthesis of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware"
Theoretical Computer Science
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
Integration, the VLSI Journal
An integrated approach to timing-driven synthesis and placement of arithmetic circuits
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Low-Power Left-to-Right Array Multiplier Design
IEEE Transactions on Computers
Design of a radix-2m hybrid array multiplier using carry save adder format
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Integrated algorithmic logical and physical design of integer multiplier
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
Transition-activity aware design of reduction-stages for parallel multipliers
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Automatic synthesis of compressor trees: reevaluating large counters
Proceedings of the conference on Design, automation and test in Europe
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Placement based multiplier rewiring for cell-based designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High performance motion estimation architecture using efficient adder-compressors
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Multiplication acceleration through twin precision
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
Dual channel addition based FFT processor architecture for signal and image processing
International Journal of High Performance Systems Architecture
Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Truncated binary multipliers with variable correction and minimum mean square error
IEEE Transactions on Circuits and Systems Part I: Regular Papers
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
Variable-latency floating-point multipliers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power efficient partial product compression
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
VHDL code generator for optimized carry-save reduction strategy in low power computer arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
Efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies
International Journal of Circuit Theory and Applications
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dependability evaluation of time-redundancy techniques in integer multipliers
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Faster and energy-efficient signed multipliers
VLSI Design
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This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1驴 CMOS ASIC technology.