Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
High performance low power array multiplier using temporal tiling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Novel Architecture for Low-Power Design of Parallel Multipliers
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Minimization of switching activities of partial products for designing low-power multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
Low power multipliers based on new hybrid full adders
Microelectronics Journal
Low-Power Multiplier Design Using a Bypassing Technique
Journal of Signal Processing Systems
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed and low-power split-radix FFT
IEEE Transactions on Signal Processing
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This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18@mm CMOS technology and 1.8V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16x16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.