Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
High performance low power array multiplier using temporal tiling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimization of switching activities of partial products for designing low-power multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-voltage micropower asynchronous multiplier with shift-add multiplication approach
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
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We describe a micropower 16×16-bit multiplier (18.8 µW/MHz @1.1 V) for low-voltage power-critical low speed (≤ 5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ∼62% and ∼79% compared to conventional 16×16-bit and 32×32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the Latch Adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from ∼5.6 and ∼10 per adder in the Adder Block in conventional 16×16-bit and 32×32-bit designs respectively to ∼2 in our designs. Based on simulations and measurements on prototype ICs (0.35 µm three metal dual poly CMOS process), we show that our 16×16-bit design dissipates ∼32% less power, is ∼20% slower but has ∼20% better energy-delay-product (EDP) than conventional 16×16-bit multipliers. Our 32×32-bit design is estimated to dissipate ∼53% less power, ∼29% slower but is ∼39% better EDP than the conventional general multiplier.