Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
High performance low power array multiplier using temporal tiling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Design by Hazard Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 0.5V 320MHz 8 bit×8 bit pipelined multiplier in 130nm CMOS process
Microelectronics Journal
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Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 µW/MHz versus 9.6 µW/MHz for 0.18-µm CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 µW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 µW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of Vdd-to-ground paths also contributes to a significant decrease of static consumption.