A 0.5V 320MHz 8 bit×8 bit pipelined multiplier in 130nm CMOS process

Authors:
Wei-Bin Yang;Chao-Cheng Liao;Yung-Chih Liang
Affiliations:
Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd, Tamsui, Taipei Hsien, Taiwan 25137, R.O.C;Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd, Tamsui, Taipei Hsien, Taiwan 25137, R.O.C;Information and Communications Research Laboratories, Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Rd., Chutung, Hsinchu, Taiwan 31040, R.O.C.
Venue:
Microelectronics Journal
Year:
2011

Citing 1
Cited 0

Transmission gates combined with level-restoring CMOS gates reduce glitches in low-power low-frequency multipliers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

This paper presents an 8x8bit pipelined multiplier operating at 320MHz under 0.5V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5V. The proposed pipelined multiplier is fabricated in 130nm CMOS process. It operates up to 320MHz and the power consumption is only 1.48mW at 0.5V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5V is reduced over 5.7 times than that of the traditional architecture at 1.2V. Thus, the proposed 8x8bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.