Lowering power in an experimental RISC processor
Microprocessors & Microsystems
Low power multipliers based on new hybrid full adders
Microelectronics Journal
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
Low power energy efficient pipelined multiply-accumulate architecture
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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A novel low power multiplication algorithm for reducing switchingactivity through operand decomposition is proposed. Ourexperimental results show 12% to 18% reduction in logic transitionsin both array multipliers and tree multipliers of 32 bits and 64bits. Similar results are obtained for dynamic power dissipationafter logic synthesis. One additional logic gate is required on thecritical path for operand decomposition, which corresponds to onlyan additional 2% to 6% of total delay in these four cases. Thus,the proposed algorithm can be applied to many digital systems wherepower consumption is a major design constraint.