Pruning fast Fourier transform algorithm design using group-based method
Signal Processing
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable VLSI architecture for FFT processor
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Reconfigurable VLSI architecture for FFT processor
WSEAS Transactions on Circuits and Systems
A reconfigurable systolic array architecture for multicarrier wireless and multirate applications
International Journal of Reconfigurable Computing
Pipeline architectures for radix-2 new Mersenne number transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems
Digital Signal Processing
A novel split-radix fast algorithm for 2-D discrete Hartley transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
PAPR reduction of OFDM using PTS and error-correcting code subblocking
IEEE Transactions on Wireless Communications
FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data
Journal of Signal Processing Systems
Distributed Arithmetic based Split-Radix FFT
Journal of Signal Processing Systems
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This paper presents a novel split-radix fast Fourier transform (SRFFT) pipeline architecture design. A mapping methodology has been developed to obtain regular and modular pipeline for split-radix algorithm. The pipeline is repartitioned to balance the latency between complex multiplication and butterfly operation by using carry-save addition. The number of complex multiplier is minimized via a bit-inverse and bit-reverse data scheduling scheme. One can also apply the design methodology described here to obtain regular and modular pipeline for the other Cooley-Tukey-based algorithms. For an N(= 2n)-point FFT, the requirements are log4 N - 1 multipliers, 4log4 N complex adders, and memory of size N - 1 complex words for data reordering. The initial latency is N + 2 · log2 N clock cycles. On the average, it completes an N-point FFT in N clock cycles. From post-layout simulations, the maximum clock rate is 150 MHz (75 MHz) at 3.3 V (2.7 V), 25°C (100°C) using a 0.35-μm cell library from Avant!. A 64-point SRFFT pipeline design has been implemented and consumes 507 mW at 100 MHz, 3.3 v, and 25°C. Compared with a radix-22 FFT implementation, the power consumption is reduced by an amount of 15%, whereas the speed is improved by 14.5%.