VLSI implementation issues for the 2-D Fermat number transform
Signal Processing
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Fast Software Encryption, Cambridge Security Workshop
Design of a high performance FFT processor based on FPGA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Research on Lossless Image Compression Algorithms Using Fermat Number Transform
SNPD '07 Proceedings of the Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing - Volume 02
Fourier Transform Computers Using CORDIC Iterations
IEEE Transactions on Computers
Discrete Convolutions via Mersenne Transrorms
IEEE Transactions on Computers
Fast algorithms for matrix multiplication usingpseudo-number-theoretic transforms
IEEE Transactions on Signal Processing
Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse
IEEE Transactions on Signal Processing
Calculation of multidimensional Hartley transforms usingone-dimensional Fourier transforms
IEEE Transactions on Signal Processing
High-speed and low-power split-radix FFT
IEEE Transactions on Signal Processing
Video filtering with Fermat number theoretic transforms using residue number system
IEEE Transactions on Circuits and Systems for Video Technology
Algorithms and pipeline architectures for 2-D FFT and FFT-like transforms
Digital Signal Processing
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Number theoretic transforms which operate in rings or fields of integers and use modular arithmetic operations can perform operations of convolution and correlation very efficiently and without round-off errors; thus, they are well matched to the implementation of digital filters. One such transform is the new Mersenne number transform, which relaxes the rigid relationship between the length of the transform and the wordlength in Fermat and Mersenne number transforms where the kernel is usually equal to a power of two. In this paper, three novel pipeline architectures that implement this transform are presented. The proposed architectures are scalable, parameterized, and can be easily pipelined; they are thus ideally suited to very high speed integrated circuit hardware-description-language (VHDL) descriptions. These architectures process data sequentially and have either one or two inputs and two or four outputs. The different input and output formats have resulted in the proposed architectures having different performances in terms of processing time and area requirements. Furthermore, they give the designer more choices in meeting the requirements of the application being implemented. A field-programmable gate array (FPGA) implementation of the proposed architectures has demonstrated that a throughput rate of up to 6.09 Gbit/s can be achieved for a 1024-sample transform, with samples coded to 31 bits.