Design of a high performance FFT processor based on FPGA

Authors:
Chu Chao;Zhang Qin;Xie Yingke;Han Chengde
Affiliations:
Institute of Computing Technology, CAS, Beijing;Institute of Computing Technology, CAS, Beijing;Institute of Computing Technology, CAS, Beijing;Institute of Computing Technology, CAS, Beijing
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

The design method of a real-time FFT processor is presented. By optimizing algorithm of memory mapping and generation of twiddle factors, a radix-4 butterfly can be calculated in one clock cycle. An approach to adaptive overflow control is also introduced to avoid overflow without interrupting the computing pipeline. The design is implemented on a FPGA chip and achieves the operating frequency at 127 MHz. It can complete a complex 1024-point FFT within 10.1 μs.