Decoupled access/execute computer architectures
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Mapping a domain specific language to a platform FPGA
Proceedings of the 41st annual Design Automation Conference
Matlab as a development environment for FPGA design
Proceedings of the 42nd annual Design Automation Conference
Design of a high performance FFT processor based on FPGA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Prediction and trace compression of data access addresses through nested loop recognition
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Efficient hardware code generation for FPGAs
ACM Transactions on Architecture and Code Optimization (TACO)
Lessons and Experiences with High-Level Synthesis
IEEE Design & Test
The iterative solver template library
PARA'06 Proceedings of the 8th international conference on Applied parallel computing: state of the art in scientific computing
Compact DFA structure for multiple regular expressions matching
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Chimpp: a click-based programming and simulation environment for reconfigurable networking hardware
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Impact of high-level transformations within the ROCCC framework
ACM Transactions on Architecture and Code Optimization (TACO)
Return to the language forrest: the case for DSL oriented software engineering
Proceedings of the FSE/SDP workshop on Future of software engineering research
Assessing Accelerator-Based HPC Reverse Time Migration
IEEE Transactions on Parallel and Distributed Systems
TARCAD: A template architecture for reconfigurable accelerator designs
SASP '11 Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors
PPMC: a programmable pattern based memory controller
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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Past research has addressed the issue of using FPGAs as accelerators for HPC systems. Such research has identified that writing low level code for the generation of an efficient, portable and scalable architecture is challenging. We propose to increase the level of abstraction in order to help developers of reconfigurable accelerators deal with these three key issues. Our approach implements domain specific abstractions for FPGA based accelerators using techniques from generic programming. In this paper we explain the main concepts behind our system to Design Accelerators by Template Expansions (DATE). The DATE system can be effectively used for expanding individual kernels of an application and also for the generation of interfaces between various kernels to implement a complete system architecture. We present evaluations for six kernels as examples of individual kernel generation using the proposed system. Our evaluations are mainly intended to provide a proof-of-concept. We also show the usage of the DATE system for integration of various kernels to build a complete system based on a Template Architecture for Reconfigurable Accelerator Designs (TARCAD).