Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
A template system for the efficient compilation of domain abstractions onto reconfigurable computers
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation. We show that integrating Matlab with HDL design tools such as HDL designer® and Precision-C® , an efficient design flow, suitable for rapid prototyping, can be obtained. The design flow accelerates process of algorithm development and simplifies test-bench formulation and verification process. The overall development time thus can be significantly reduced. We elaborate on the advantages and disadvantages of the design flow. It will be shown that Matlab based design flow generates functional specifications that are useful for RTL development.