Matlab as a development environment for FPGA design
Proceedings of the 42nd annual Design Automation Conference
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Introduction to High-Level Synthesis
IEEE Design & Test
Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking
ICCTD '09 Proceedings of the 2009 International Conference on Computer Technology and Development - Volume 01
Exploring the concurrency of an MPEG RVC decoder based on dataflow program analysis
IEEE Transactions on Circuits and Systems for Video Technology
MMSys '10 Proceedings of the first annual ACM SIGMM conference on Multimedia systems
Software Code Generation for the RVC-CAL Language
Journal of Signal Processing Systems
Synthesizing Hardware from Dataflow Programs
Journal of Signal Processing Systems
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Run-length encodings (Corresp.)
IEEE Transactions on Information Theory
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current MPEG coding technologies using a dataflow language called Cal Actor Language (CAL). CAL is associated with a set of tools to design dataflow applications and to generate hardware and software implementations. Before this work, the existing CAL hardware compilers did not support high-level features of the CAL. After presenting the main notions of the RVC standard, this paper introduces an automatic transformation process that analyses the non-compliant features andmakes the required changes in the intermediate representation of the compiler while keeping the same behavior. Finally, the implementation results of the transformation on video and still image decoders are summarized. We show that the obtained results can largely satisfy the real time constraints for an embedded design on FPGA as we obtain a throughput of 73 FPS for MPEG 4 decoder and 34 FPS for coding and decoding process of the LAR coder using a video of CIF image size. This work resolves the main limitation of hardware generation from CAL designs.