Matlab as a development environment for FPGA design
Proceedings of the 42nd annual Design Automation Conference
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
FPGA implementation of an MUD based on cascade filters for a WCDMA system
EURASIP Journal on Applied Signal Processing
An efficient circulant MIMO equalizer for CDMA downlink: algorithm and VLSI architecture
EURASIP Journal on Applied Signal Processing
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In this paper, an efficient design flow integrating MentorGraphics Precesion C and HDL designer is derived. In thishybrid prototyping environment, efficient FPGA architecturesare scheduled rapidly with specific hardware resource/timing/architecture constraints from C/C++ levelmodeling by allocating the usage of functional units andreal-time requirements. Using this methodology, a systemon-chip architecture for the next-generation CDMA system,i.e., HSDPA system, is prototyped rapidly. Advanced algorithmsincluding chip-level equalizer, turbo codec and clocktracking, frequency offset compensation, are scheduled withPrecesion C. A relatively more area/timing efficient RTLarchitecture is generated automatically and integrated withother design blocks in HDL designer, then implementedefficiently in Xilinx FPGAs. This new design flow demonstratesproductivity improvement of 2X for typical wirelesscommunication algorithms and reduces the risk of productdevelopment dramatically.