IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional verification of large ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
High performance and low power FIR filter design based on sharing multiplication
Proceedings of the 2002 international symposium on Low power electronics and design
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
A DSP-based DS-CDMA multiuser receiver employing partial parallel interference cancellation
IEEE Journal on Selected Areas in Communications
Adaptive multistage parallel interference cancellation for CDMA
IEEE Journal on Selected Areas in Communications
Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems
Journal of Signal Processing Systems
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In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from $\mathcal{O}(K^2N)$ to $\mathcal{O}(KN)$. The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least $10 \times$saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least $4 \times$speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to $90 \%$