Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Journal of VLSI Signal Processing Systems
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
WCDMA uplink parallel interference cancellation: system simulations and prototype field trials
EURASIP Journal on Applied Signal Processing
Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems
Journal of Signal Processing Systems
Application of fuzzy logic for adaptive interference canceller in CDMA systems
IEA/AIE'07 Proceedings of the 20th international conference on Industrial, engineering, and other applications of applied intelligent systems
Statistical-mechanical approach for multiple watermarks using spectrum spreading
ICITS'09 Proceedings of the 4th international conference on Information theoretic security
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The implementation of advanced DS-CDMA receivers based on multiuser detection principles is becoming a reality thanks to the combination of an improved understanding of the theoretical basis of multiuser detection and advances in digital, mixed-signal, and RF technologies. Due to their lower complexity, subtractive interference cancellation approaches are attractive for the practical implementation of multiuser detection. In a parallel interference cancellation receiver, it is practical to use the soft outputs of a matched filter bank for amplitude estimation. A bias arises in the decision statistics, however, due to imperfect estimation and interference cancellation. In this paper, the source of the bias is explicitly recognized, and a partial interference cancellation scheme that mitigates the negative effects of biased estimation and significantly improves system performance is proposed. A practical real-time algorithm that significantly reduces the implementation complexity of this scheme without sacrificing performance is then derived. To facilitate a software radio implementation, the signal processing complexity of the approach is characterized. The real-time processing algorithm is tested via implementation in software on a floating-point general-purpose DSP. The prototype includes a flexible software-based architecture which performs IF sampling and uses digital downconversion prior to baseband processing. The hardware test setup is described, and the results are presented and compared with simulation and analytical results. The experimental results confirm the simulation and analytical results which show large performance gains over the conventional matched filter