Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers

Authors:
Sridhar Rajagopal;Srikrishna Bhashyam;Joseph R. Cavallaro;Behnaam Aazhang
Affiliations:
Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, USA;Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, USA;Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, USA;Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, USA
Venue:
Journal of VLSI Signal Processing Systems
Year:
2002

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Abstract

This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband processing operations in wireless base-station receivers for CDMA. Future wireless base-station receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP implementations of these algorithms are unable to meet real-time requirements. However, there exists massive parallelism and bit level arithmetic present in these algorithms than can be revealed and efficiently implemented in a VLSI architecture. We re-design an existing channel estimation algorithm from an implementation perspective for a reduced complexity, fixed-point hardware implementation. Fixed point simulations are presented to evaluate the precision requirements of the algorithm. A dependence graph of the algorithm is presented and area-time trade-offs are developed. An area-constrained architecture achieves low data rates with minimum hardware, which may be used in pico-cell base-stations. A time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data processing rates. An area-time efficient architecture meets real-time requirements with minimum area overhead.