Functional verification of large ASICs

Authors:
Adrian Evans;Allan Silburt;Gary Vrckovnik;Thane Brown;Mario Dufresne;Geoffrey Hall;Tung Ho;Ying Liu
Affiliations:
Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada;Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex.