Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification of large ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Verifying large-scale multiprocessors using an abstract verification environment
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Functional verification of the equator MAP1000 microprocessor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A study in coverage-driven test generation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Art of Verification with VERA
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Coverage-oriented verification of banias
Proceedings of the 40th annual Design Automation Conference
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Proceedings of the 41st annual Design Automation Conference
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A method for the evaluation of behavioral fault models
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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As an industrial practice, the functional coverage models are developed based on a high-level specification of the Design Under Verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed entirely from a high-level specification. We present a method to automatically generate implementation-aware coverage models based on the static analysis of a HDL description of the DUV. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.