Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
Digital Technical Journal - Special 10th anniversary issue
Verifying a Multiprocessor Cache Controller Using Random Test Generation
IEEE Design & Test
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A C-based RTL design verification methodology for complex microprocessor
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Virtual chip: making functional models work on real target systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Functional verification of the equator MAP1000 microprocessor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Alpha 21164 Manufacturing Test Development and Coverage Analysis
IEEE Design & Test
Postsilicon Validation Methodology for Microprocessors
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Coverability Analysis Using Symbolic Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
TABLEAUX '99 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Improvements in Coverability Analysis
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Practical concurrent ASIC and system design and verification
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
MANUFACTURING PATTERN DEVELOPMENT FOR THE ALPHA 21164 MICROPROCESSOR
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Refactoring digital hardware designs with assertion libraries
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Proceedings of the conference on Design, automation and test in Europe
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
A transaction-based unified architecture for simulation and emulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using coverage to deploy formal verification in a simulation world
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Planning for end-to-end formal using simulation-based coverage: invited tutorial
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Assertion-Based verification for the SpaceCAKE multiprocessor – a case study
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Targeted random test generation for power-aware multicore designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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