Innovative verification strategy reduces design cycle time for high-end SPARC processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Software development in a hardware simulation environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Virtual chip: making functional models work on real target systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification of large ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
UNIX Network Programming: Networking APIs: Sockets and XTI
UNIX Network Programming: Networking APIs: Sockets and XTI
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Exploring SW Performance Using SoC Transaction-Level Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Hi-index | 0.00 |
The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This paper describes a layered architecture suitable for both simulation and emulation. The architecture uses transactions for communication and synchronization between the driving environment (DE) and the device under test (DUT). Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators. The result is more efficient development of the DE and 100% portability when moving from simulation to emulation. We give an overview of our layered architecture and describe its implementation. Our results show that, by using emulation, the Register-Transfer level (RTL) implementation of an industrial design can be verified in the same amount of time it takes to run a C-based simulation. We also show two orders of magnitude speeds up over simulations of C and RTL through a programming language interface.