Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
System Design: Traditional Concepts and New Paradigms
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dynamic and formal verification of embedded systems: a comparative survey
International Journal of Parallel Programming
A smooth refinement flow for co-designing HW and SW threads
Proceedings of the conference on Design, automation and test in Europe
A cosimulation methodology for HW/SW validation and performance estimation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A transaction-based unified architecture for simulation and emulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
VLSI Design - Special issue on Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications
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This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the SoC platform. The SoC provider provides a cycle-accurate functional model of the SoC architecture using the basic SystemC Transaction Level Modeling (TLM) components provided by VISTA : bus models, memories, IPs, CPUs, and RTOS generic services. These components have been carefully designed to be integrated into a SoC design flow with an implementation path for automatic generation of IP HW interfaces and SW device drivers. The application developer can then integrate the application code onto the SoC architecture as a set of SystemC modules. VISTA supports cross-compilation on the target processor and back annotation, therefore bypassing the use of an ISS. We illustrate the features of VISTA through the design and simulation of an MPEG video decoder application.