On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
VHDL design representation and synthesis (2nd ed.)
VHDL design representation and synthesis (2nd ed.)
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Proceedings of the 37th Annual Design Automation Conference
embedded system design with multiple languages: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
The Complete VERILOG Book
Art of Software Testing
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
Computer
System-on-a-Chip Cosimulation and Compilation
IEEE Design & Test
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Hierarchical Modeling and Verification of Embedded Systems
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Ambient intelligence: a computational platform perspective
Ambient intelligence
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring SW Performance Using SoC Transaction-Level Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Transaction Level Modeling: Flows and Use Models
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Coverage of Formal Properties Based on a High-Level Fault Model and Functional ATPG
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Timed HW-SW cosimulation using native execution of OS and application SW
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
MTV '05 Proceedings of the Sixth International Workshop on Microprocessor Test and Verification
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The development of more and more complex embedded systems constitutes a very challenging task for EDA experts, due to their HW/SW-mixed nature joint to the high demand for quality and reliability. Recently, both industrial engineers and academic researchers have developed a very large number of techniques for dynamic verification in terms of co-simulation, which, in particular, address the different nature of hardware and software components of an embedded system. However, a widely accepted methodology does not exist. Thus, this paper is intended to provide a general view on simulation-based modeling and verification strategies for developing embedded systems. In particular, the paper is focussed on describing state-of-the art co-simulation approaches and verification strategies based on fault simulation and assertion checking.