Hierarchical Modeling and Verification of Embedded Systems

Authors:
Luis Alejandro Cortés;Petru Eles;Zebo Peng
Affiliations:
-;-;-
Venue:
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Year:
2001

Citing 0
Cited 4

Modeling and formal verification of embedded systems based on a Petri net representation

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Accelerating design space exploration using pareto-front arithmetics

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Dynamic and formal verification of embedded systems: a comparative survey

International Journal of Parallel Programming
Hardware design and simulation for verification

SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Abstract: In order to represent efficiently large systems, a mechanism for hierarchical composition is needed so that the model may be constructed in a structured manner and composed of simpler units easily comprehensible by the designer at each description level. In this paper we formally define the notion of hierarchy for a Petri net based representation used for modeling embedded systems. We show how small parts of a large system may be transformed by using the concept of hierarchy and the advantages of a transformational approach in the verification of embedded systems. A real-life example illustrates the feasibility of our approach on practical applications.