An architecture for exploring large design spaces
AAAI '98/IAAI '98 Proceedings of the fifteenth national/tenth conference on Artificial intelligence/Innovative applications of artificial intelligence
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the conference on Design, automation and test in Europe
Hierarchical Modeling and Verification of Embedded Systems
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded processors and systems: Architectural issues and solutions for emerging applications
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Initial population construction for convergence improvement of MOEAs
EMO'05 Proceedings of the Third international conference on Evolutionary Multi-Criterion Optimization
Divide and conquer high-level synthesis design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Compositional system-level design exploration with planning of high-level synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose an approach for the synthesis of heterogeneous (embedded) systems, while exploiting a hierarchical problem structure. Particular to our approach is that we explore the set of so-called Pareto-optimal solutions, i.e., optimizing multiple objectives simultaneously. Since system complexity grows steadily leading to giant search spaces which demand for new strategies in design space exploration, we propose Pareto-Front Arithmetics (PFA) using results of subsystems to construct implementations of the top-level system. This way, we are able to reduce the exploration time dramatically. An example of an MPEG4 coder is used to show the benefit of this approach in real-life applications.