High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
High-level synthesis scheduling and allocation using genetic algorithms
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Performing Scheduling and Storage Optimization Simultaneously Using Genetic Algorithms
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
Accelerating design space exploration using pareto-front arithmetics
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient design space exploration for application specific systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal
Methods for power optimization in SOC-based data flow systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A family of compact genetic algorithms for intrinsic evolvable hardware
IEEE Transactions on Evolutionary Computation
A genetic algorithm for the design space exploration of datapaths during high-level synthesis
IEEE Transactions on Evolutionary Computation
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Datapath synthesis using a problem-space genetic algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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High level synthesis has now almost become an industry de facto standard for designing Application Specific Processors (ASPs) and Application Specific Integrated Circuits (ASICs). High level synthesis (HLS) designing requires an efficient exploration approach with the ability to determine optimal/near-optimal scheduling solutions and module selection with significant speed and precision. A novel exploration approach using the 'S-value' method that reduces the final power dissipation of the solution using minimal control step is presented in this paper. This approach is based on the proposed 'Primacy Selector (S-value)' metric and 'Intersect Matrix' topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Two novel aspects discussed in this paper are: (a) introduction of 'Intersect Matrix' topology with its associated algorithm, which is used to check for precedence violation during scheduling, (b) introduction of S-value method metric, which assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach is done with an existing design space exploration method for qualitative assessment using proposed 'Quality Cost Factor (Q-metric)'. An average improvement of approximately 5.07% in quality of final scheduling solution and average reduction of 59% in exploration runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.