Efficient algorithms for acceptable design exploration
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
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This paper presents a method for performing scheduling and allocation of functional units simultaneously with storage optimization in high-level synthesis using Genetic Algorithms. The method involves augmenting a standard CDFG with storage operations and scheduling these operations on available storage units. The resulting synthesis tool is flexible and can support any type of storage units from registers, to multi-port register files and memories. Results on typical circuits and benchmarks prove the flexibility and performance of this technique.