Synthesis of embedded software using free-choice Petri nets
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Convex Optimization
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
Accelerating design space exploration using pareto-front arithmetics
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A calculator for Pareto points
Proceedings of the conference on Design, automation and test in Europe
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Computational Geometry: Algorithms and Applications
Computational Geometry: Algorithms and Applications
Industrial IP integration flows based on IP-XACT™ standards
Proceedings of the conference on Design, automation and test in Europe
High-Level Synthesis: Past, Present, and Future
IEEE Design & Test
A compositional modelling framework for exploring MPSoC systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Design space exploration acceleration through operation clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Proceedings of the 47th Design Automation Conference
Decision-theoretic design space exploration of multiprocessor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Supervised design space exploration by compositional approximation of Pareto sets
Proceedings of the 48th Design Automation Conference
A method to abstract RTL IP blocks into C++ code and enable high-level synthesis
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration we present three main contributions: a concise library format for characterization and reuse of components specified in high-level languages like SystemC; an algorithm to prune alternative implementations of a component given the context of a specific SoC design; and an algorithm that explores compositionally the design space of the SoC and produces a detailed plan to run high-level synthesis on its components for the final implementation. The two algorithms are computationally efficient and enable an effective parallelization of the synthesis runs. Through a case study, we show how our methodology returns the essential properties of the design space at the system level by combining the information from the library of components and by identifying automatically those having the most critical impact on the overall design.