A scheduling and pipelining algorithm for hardware/software systems
ISSS '97 Proceedings of the 10th international symposium on System synthesis
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
Proceedings of the 6th international workshop on Hardware/software codesign
COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
The D30V/MPEG Multimedia Processor
IEEE Micro
SuperENC: MPEG-2 Video Encoder Chip
IEEE Micro
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
System-level codesign of mixed hardware-software systems
System-level codesign of mixed hardware-software systems
Flexibility/Cost-Tradeoffs of Platform-Based Systems
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Flexibility/cost-tradeoffs of platform-based systems
Embedded processor design challenges
Algorithmic aspects of hardware/software partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accelerating design space exploration using pareto-front arithmetics
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
HW/SW partitioning using discrete particle swarm
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Finding optimal hardware/software partitions
Formal Methods in System Design
Hardware/software partitioning with multi-version implementation exploration
Proceedings of the 18th ACM Great Lakes symposium on VLSI
RRES: a novel approach to the partitioning problem for a typical subset of system graphs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
A polynomial algorithm for partitioning problems
ACM Transactions on Embedded Computing Systems (TECS)
Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
International Journal of Applied Mathematics and Computer Science
Solving partitioning problem in codesign with ant colonies
IWINAC'05 Proceedings of the First international work-conference on the Interplay Between Natural and Artificial Computation conference on Artificial Intelligence and Knowledge Engineering Applications: a bioinspired approach - Volume Part II
Automatic generation of hardware/software interfaces
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
| Hi-index | 0.00 |
The paper presents MAGELLAN, a heuristic technique for mapping hierarchical control-dataflow task graph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user. The objective of the technique is to minimize the worst case latency of the task graph subject to the area constraints on the architecture. The technique uses an iterative approach consisting of closely linked hardware-software partitioner and scheduler. Both the partitioner and scheduler operate on the task graph in a hierarchical top down manner. The technique optimizes deterministic loop constructs by applying clustering, unrolling and pipelining. The technique considers speculative execution for conditional constructs. The number of actual hardware/software implementations of a function in the task graph are also optimized by the technique. The effectiveness of the technique is demonstrated by a case study of an image compression algorithm.