DATE '99 Proceedings of the conference on Design, automation and test in Europe
IEEE Micro
A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An MPEG2-Based Digital CATV and VOD System using ATM-PON Architecture
ICMCS '96 Proceedings of the 1996 International Conference on Multimedia Computing and Systems
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the ninth international symposium on Hardware/software codesign
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System
ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Journal of VLSI Signal Processing Systems
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
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This article demonstrates the flexibility and usefulness of SuperENC, an architecture for a single-chip MPEG-2 video encoder. The architecture, based on three-layer cooperation, provides flexible data transfer that improves the encoder's versatility, scalability, and video quality. The LSI chip was successfully fabricated in the 0.25-micron, four-metal CMOS process. Its small size and low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC card encoders, and HDTV encoders.